Meet the SERDES challenge: Design a high-speed serial backplane

Increasing chip-to-chip, board-to-board, and system-to-system communications data rates have created the need for multi-gigabit asynchronous signaling schemes in which serializer/deserializer (SERDES) technology is used to format and transfer data.
View the full article HERE

Tags: system communications, high speed, chip board, serial backplane

• Categories

  • Admin
  • Chip Road
  • Design and Reuse
  • IC Design
  • Latest IP info
  • SemiWiki

• Archives

  • May 2013
  • April 2013
  • March 2013
  • February 2013
  • January 2013
  • December 2012
  • November 2012
  • October 2012
  • September 2012
  • August 2012
  • July 2012
  • June 2012
  • May 2012
  • April 2012
  • March 2012
  • February 2012
  • January 2012
  • December 2011
  • November 2011
  • October 2011
  • September 2011
  • August 2011
  • July 2011
  • June 2011
  • May 2011
  • April 2011
  • March 2011
  • February 2011

• IP Vendor

  • ASICS.ws
  • Chips and Media
  • Core Works
  • Digital Core Design
  • ExpertIO.Inc
  • IPextreme
  • IPGenius
  • IPreuse Tool
  • Silicon IP

• Related Links

  • Chips Estimate
  • Design and Reuse
  • GSA
  • IPcore BBS
  • OCP-IP
  • Open Cores
  • Open Virtual Platforms
  • SemiWiki
  • Synopsys IPreuse Tool

• Contact

  admin@ipreuse.org

• Tag Cloud

  arasan chip systems china mobile china telecom cooperative partner data storage dolphin integration energy consumption executive vice few days first quarter fourth quarter full article full IP Description future generation hard disk hard disks hewlett packard high density high performance high speed host computer large scale long time magnetic disc market share medium sized enterprises mentor graphics million dollars mips technologies mobile phone new generation next generation operating system pci express power consumption real time science and technology second quarter silicon image small and medium sized enterprises storage equipment storage system two kinds vice president wide margin

• Recent Posts

  • WLAN 2×2 MIMO MAC/Baseband 802.11 ac
  • WLAN 2×2 MIMO MAC/Baseband 802.11 ac
  • Streaming pipelined FFT
  • Streaming pipelined FFT
  • DRC debugging challenges in AMS/custom designs at 20 nm
  • Dolphin Integration announces a new generation of ultra-dense standard cell library for GSMC 0.18 mm uLL eFlash process
  • Penetration of Verification IP
  • Synopsys Delivers VDK for Renesas RH850 MCUs
  • Cisco Completes Acquisition of Ubiquisys
  • Cadence Completes Acquisition of Cosmic Circuits

• Random Posts

  • The Importance of True Randomness in Cryptography
  • TSMC's R&D chief sees 10 years of scaling
  • Arasan Chip Systems Releases Universal Flash Storage (UFS) 1.1 IP
  • Xelic Announces 40G I.4/I.7 EFEC Core
  • Building a NAND flash controller with high-level synthesis
  • IC Knowledge's Cost Modeling of Semiconductor Manufacturing Shows Fully Depleted Silicon-on-Insulator Technology to be the Most Cost-effective Approach at the 22nm Node
  • Where the Smart Money Goes in Semiconductors
  • apb_slave_vmt from Synopsys

• Recent Comments

  • Sangyoub Lee on Adaptive Digital Front-End (DDC/DUC/CFR/DPD) for LTE/GSM/WCDMA from ElementCXI
  • SENGUTTUVAN on Analog Layout Design Training in India (Bangalore)
  • Susan on eSilicon adds Wim Roelandts and Timothy Chen to its Board; Appoints Seth Neiman as Chairman
  • amit kumar keshari on Analog Layout Design Training in India (Bangalore)
  • We Sell Quality Electronics And Cell Phones Online! on Designing a high-definition FPGA-based graphics controller