HercuLeS is named after the homonymous constellation and not after the demigod.
You can find information on HercuLeS here:
Nikolaos Kavvadias – HercuLeS high-level synthesis tool
A very informative blog post can be found at EETimes: HercuLeS, High-Level Synthesis, HLS, Nikolaos Kavvadias | Introducing a new high-level synthesis tool called HercuLeS
Some of its features:
1. Integer and fixed-point (VHDL-2008) arithmetic of arbitrary lengths
2. It is able to synthesize VHDL from code spanning across several C functions
3. Support for both the Synopsys “de-facto standard” libraries and the official IEEE standard libraries
4. Support of synchronous read ROM and RAM memories (directly mapped to FPGA block RAMs)
5. Functions can pass single-dimensional array arguments
6. Support of streaming outputs (producing a sample at a time)
You can either code your input in ANSI C or in a bit-accurate typed-assembly language called NAC (N-Address Code). Then, your input is converted to a series of CDFGs (Control/Data Flow Graphs), expressed as Graphviz graphs with user-defined attributes, which again are translated to VHDL code adhering to the FSMD (Finite-State Machine with Datapath) paradigm.
I would appreciate if you had a look at the sample files available at the website. They illustrate complete examples of automatically synthesized algorithms such as Bresenham’s line drawing algorithm, and the Sieve of Eratosthenes. Overall, eight complete examples can be found at the HercuLeS website.
There will be regular updates on the HercuLeS webpage (every 1-1.5 months). The October update, scheduled for 2011/10/11, will allow access to HercuLeS via a web interface!
But first I would appreciate feedback on whatever related to the HercuLeS webpage.
You can contact me at: nikolaos.kavvadias-at-gmail-dot-com.
Research Scientist, Hardware developer,
Ph.D., M.Sc., B.Sc.
Compact 8051 Microcontroller – complex Finite State Machine Applications