LG Electronics Accelerates Analog Simulation by 10X with Synopsys CustomSim
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Tags: analog simulation
The Discovery Verification Platform is an integrated portfolio of functional, AMS, formal, low-power and hardware-assisted verification tools. Discovery provides high performance, high accuracy and efficient interactions among best-in-class technologies including mixed-HDL simulation, mixed-signal simulation, assertions, coverage, testbench automation, verification IP, formal analysis, unified debug, equivalence checking and rapid prototyping. Discovery’s components support industry standards including SystemVerilog, SystemC, VHDL, UPF, OpenVera, Verilog-A, Verilog-AMS, SPICE, and more.
| | Using Digital Verification Techniques on Mixed-signal SoCs with CustomSim and VCS |
| | Graeme Nunn, Calvatec; Fabien Delguste, Adiel Khan, Abhisek Verma, Bradley Geden, Synopsys
A case study that explains the various aspects of a scalable and reusable methodology for verifying analog IP that can be applied to VMM/UVM, from verification planning to testbench implementation and coverage collection. |
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| | Accelerating Analog Simulation with HSPICE Precision Parallel Technology |
| | Robert Daniels, Sr. Staff Engineer, Synopsys Inc.; Harald Von Sosen, Principal Engineer, Synopsys Inc.; Hany Elhak, Product Marketing Manager, Synopsys Inc.
HSPICE Precision Parallel technology is a new multicore transient simulation extension to HSPICE for both pre- and post-layout of complex analog circuits such as PLLs, ADCs, DACs, SERDES, and other full mixed-signal circuits. HPP addresses the traditional bottleneck in accelerating SPICE on multicore CPUs with new algorithms that enable a larger percentage of the simulation to be parallelized, with no compromise in golden HSPICE accuracy. Additionally, efficient memory management allows simulation of post-layout circuits larger than 10 million elements. |
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| | High-performance, Parallel Simulation with VCS Multicore Technology |
| | This white paper provides a detailed overview of VCS multicore technology, which improves verification performance by taking advantage of advances in the compute infrastructure. VCS multicore technology cuts verification time in half by harnessing the power of modern multicore CPUs and allows designers to identify performance bottlenecks and distribute time-consuming activities across multiple cores for faster functional verification and debug. Automatic partitioning and load balancing, event synchronization and memory optimization make VCS multicore unique for high-performance functional verification. Multicore technology combines the speed-up from parallel computation with the industry-leading Native Testbench (NTB) compiler optimization technique to deliver unmatched verification performance for large-scale designs for chip-level and system-level verification.
Usha Gaira and Sanjay Sawant |
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| | Are We There Yet |
| | How do you know when you have run enough random tests? A constraint-driven random environment requires comprehensive coverage data, which often leads to information overload. Without an automatic way to associate pieces of coverage data with a particular feature-set in the test plan, the coverage report is only meaningful to the creator of the data.
Nancy Pratt Dwight Eddy |
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| | A Fully Reusable Register/Memory Access Solution: Using VMM RAL |
| | Register structure and memory modeling is a very complex task of any verification methodology. Building a zero time mirror to check the correct functionality of every field from every register and memory is usually a very time-consuming process which needs to be repeated for every design.
Paul Lungu, |
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| | Five Vital Steps to a Robust Testbench with DesignWare Verificatio IP |
| | Verification is one of the biggest challenges for System-on-Chip (SoC) designs, and traditional methods have run out of steam. Writing individual tests is impractical for today’s large, complex designs because the state space and number of test conditions is simply too large to code by hand, leading to insufficient test coverage.
Charles Li, Ashesh Doshi |
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| | Low Power Verification for Multi-rail Cells |
| | Multi-voltage designs have become increasingly common in order to achieve low power. Multiple supply rails are an essential part of multi-voltage designs. Assuming that all output pins in a logic cone are related to a single supply voltage can cause functional failures in silicon or excessive power loss. Consequently, verification tools need to understand the relationship between the driving voltage rails and the impact on each output pin to accurately resolve the logic values. Synopsys’ Eclypse solution provides an infrastructure to capture the necessary information and MVSIM and MVRC are able to use the information to accurately verify multi-rail designs and lead to silicon success. This white paper discusses the challenges faced with static and dynamic verification of multi-rail cells in the context of low power designs.
Prapanna Tiwari, Synopsys, Inc. |
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| | NanoSim: A Next-generation Solution for SoC Integration Verification |
| | The convergence of consumer electronics and personal computing continues to drive the need for more powerful, complex and highly integrated IC design, fabricated with the latest manufacturing technologies.
Geoffrey Ying |
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| | SystemVerilog for e Experts |
| | This document identifies the major differences between the e language as defined by the IEEE P1647/ D6 draft standard and the SystemVerilog language as defined by the IEEE Std. 1800™ 2005 standard. It explains the semantics of those differences and, where relevant, presents how similar functionality can be obtained using SystemVerilog.
Janick Bergeron Synopsys Scientist |
Tags: transient simulation, robert daniels, verification platform, analog ip, digital verification, layout circuits