Die-to-die bonding using copper pillars
An update on the advantages of copper pillar bumps over conventionally used solder bumps; copper…
MIPI LLI IP Core
MIPI LLI IP Core
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Tags: full IP Description, MIPI LLI
SuperSpeed USB 3.0 PHY
SuperSpeed USB 3.0 PHY
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Designing embedded SoCs using older resistive technologies
When designing an SoC with a generic 32-bit MCU based on 0.18um (180 nm) processes with flash and a rich suite of analog and digital IPs, the authors found that the pre-route engines from current EDA tool vendors are tuned for smaller transistor node sizes and are not very good at the larger 180 nm geometries. Here are the steps they took to overcome such problems.
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Tags: rich suite, EDA tool vendors
Insufficient baseband chip supply hurting LTE smartphone sales
Insufficient baseband chip supply hurting LTE smartphone sales
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Tags: LTE smartphone
Why chip makers are buying software firms
Why chip makers are buying software firms
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Analog Bits Unveils Integrated Sensor Macro Family
Analog Bits Unveils Integrated Sensor Macro Family
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Xtendwave selects EnSilica’s eSi-3200 processor for the receiver IC implementing NIST’s next-generation WWVB atomic timekeeping signal
Xtendwave selects EnSilica’s eSi-3200 processor for the receiver IC implementing NIST’s next-generation WWVB atomic timekeeping signal
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Tags: receiver IC
8051 Microcontroller IP Cores from CAST Even More Efficient with New Single-Wire Debug
8051 Microcontroller IP Cores from CAST Even More Efficient with New Single-Wire Debug
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Tags: 8051 microcontroller, 8051 Microcontroller IP Cores
Xilinx Ships World’s First Heterogeneous 3D FPGA
Xilinx Ships World’s First Heterogeneous 3D FPGA
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Tags: Xilinx Ships