Arasan Chip Systems Announces 3rd Generation Hardware Validation Platform Family for Mobile Interface Standards
Arasan Chip Systems Announces 3rd Generation Hardware Validation Platform Family for Mobile Interface Standards
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Tags: Chip Systems Announces 3rd Generation, 3rd Generation Hardware Validation, Arasan Chip Systems Announces, Mobile Interface StandardsView
Picking the Right Driver
In this release, our focus has been on optimizing the VP8 bitstream decoder. The new architecture helps the IP run at 13% higher operating frequency allowing the decoder chips to reach higher frame rates or do multi-channel decoding more easily. At the same time, the new implementation has reduced the decoder’s logic gate count by 6% which directly cuts the production cost of each chip incorporating a WebM hardware decoder. Furthermore, the revamped design allows us to do even more optimizations for the next release. With future video requirements in mind, we designed Driver to decode up to 4k by 4k video resolutions.
To make the IP evaluation easier for a chip company, the deliverables now include a bit-exact decoder C-model. This allows partners to create their own test cases for thorough performance analysis.
Modern multi-core CPUs are getting powerful enough to decode HD video, so why is having hardware accelerators still useful? One good reason is battery life. We got our hands on one of the first commercial Android tablets based on the Rockchip RK2918 chip which uses our very own WebM hardware decoder and ran some tests. We charged the battery and looped a 480p video until the battery died. For the purpose of the experiment, we had to limit the resolution because the single-core CPU of the device could not run 720p @ 30fps in pure software. The battery test was done with the VP8 hardware acceleration enabled and disabled, and at two display brightness settings. The result: with the hardware offload the battery lasted up to 36% longer which gets us one extra movie to watch on that long flight! You can see the battery discharge vs. elapsed time plots below. Needless to say, using two or four CPU cores for HD video decoding in software uses even more power and widens the gap to hardware’s benefit.
The G1 v4 VP8 decoder is now available for licensing at no cost at the WebM Project hardware page. The multiformat version of the IP and support services can be accessed through our partner Verisilicon.
Aki Kuusela is Engineering Manager of the WebM Project hardware team.
Tags: IP evaluation, hardware decoder, chip company
14-Bit 300MHz ADC in TSMC 65nm G from Cadence
14-Bit 300MHz ADC in TSMC 65nm G from Cadence
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Tags: Cadence View
802.11a Physical Layer Baseband from Ingenieurburo BAY9
802.11a Physical Layer Baseband from Ingenieurburo BAY9
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Tags: Physical Layer, Physical Layer Baseband
DDR DLL PHY – 8 Bit Slice – TSMC 40LP from Cadence
DDR Hardened 8-bit data/address/control Slice for DDR DLL PHY (must be combined with IO\s and ESD) – supports up to DDR1066
Xilinx Ships First Zynq-7000 Devices, the World’s First Extensible Processing Platform
Xilinx Ships First Zynq-7000 Devices, the World’s First Extensible Processing Platform
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Synopsys’ IC Validator Certified by GLOBALFOUNDRIES for 28-nm, 40-nm and 65-nm Design
Synopsys’ IC Validator Certified by GLOBALFOUNDRIES for 28-nm, 40-nm and 65-nm Design
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Tags: IC Validator
Ikanos Communications Selects eSilicon For Manufacturing Operations and Logistics
Ikanos Communications Selects eSilicon For Manufacturing Operations and Logistics
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Tags: Manufacturing Operations, Ikanos Communications
AutoCAD2010完全自学教程 【B超读片手册 】
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多媒体光盘内容为实例的素材、源文件及520段语音教学视频。
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出版社: 北京希望电子出版社; 第1版
平装: 477页
正文语种: 简体中文
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条形码: 9787894989727
商品尺寸: 25.8 x 19.8 x 2.4 cm
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ASIN: B003981LO4
AutoCAD2010完全自学教程(附DVD-ROM光盘1张)
B超读片手册
《B超读片手册》主要内容有：超声诊断原理、甲状腺疾病、乳腺疾病、正常超声心动图、瓣膜病、心肌病、高血压性心脏病、冠状动脉粥样硬化性心脏病等。
出版社: 军事医学科学出版社; 第1版
丛书名:影像学读片掌中宝系列
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条形码: 9787801219459
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ASIN: B0011BZ3HC
Mark Horowitz to Step Down From Rambus Board of Directors
Mark Horowitz to Step Down From Rambus Board of Directors
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Tags: Mark Horowitz, board of directors