Mixed-signal SOC verification using analog behavioral models
Bringing analog and mixed-signal blocks to a higher abstraction level yields more effective mixed-signal simulation and more complete
verification environments.
Tags: abstraction level
Understanding the concept of X in SOC design flow
The concept of “X,” “X corruption,” and “X propagation” has been intriguing to many design engineers. This article focuses on giving an idea about these terms, reasons for the occurrence of X, the impacts it causes and some best practices to follow to avoid any undesirable effects.
Tags: undesirable effects, design engineers
Sponsored Link: Learn analog systems with TI’s Analog System Lab Kit
Designed for undergraduate engineering students, the ASLK PRO features 14 step-by-step experiments using analog ICs. Apply for a donation of up to 10 ASLK boards for your University.
Tags: undergraduate engineering, analog ICs
Resolving timing miscorrelation using timing uncertainties
The suggested strategy solves the miscorrelation problem between the timing and the optimization tools in a way that helps avoid extra pessimism in the design, thus saving on area and power.
Developing high-frequency integrated circuits for test and measurement
The development of high-frequency circuits is very demanding, in multiple dimensions; not least, in order to meet tight time-to-market schedules, the use of efficient development systems is a must.
Tags: integrated circuits, development systems
Pitfalls to avoid in SoC clocking
Optimal clock structure is very important in SoC designs as it impacts every critical aspect of the IC. The article explains multiple such scenarios that VLSI designers need to be aware of while architecting or analyzing the SoC clocking in ASIC designs.
Tags: critical aspect
Is high-level synthesis ready for prime time?
After years of promises that next year would be the year of ESL design, the knee of the curve is now behind us, EDA analyst Gary Smith declared at this year’s DAC.
Tags: gary smith
ARM CTO asks: Are we getting value from verification?
Low power is not an absolute but is context-dependent, ARM CTO Mike Muller says.
EDA lost in the clouds?
Vendors and customers go slowly on cloud computing.
Pseudo hardening in SoC design
Handling late-stage IPs with a pseudo-hardening approach offers the best of both the ‘flat-’ and ‘hard-partitioning’ methodologies