Bringing analog and mixed-signal blocks to a higher abstraction level yields more effective mixed-signal simulation and more complete
The concept of “X,” “X corruption,” and “X propagation” has been intriguing to many design engineers. This article focuses on giving an idea about these terms, reasons for the occurrence of X, the impacts it causes and some best practices to follow to avoid any undesirable effects.
Designed for undergraduate engineering students, the ASLK PRO features 14 step-by-step experiments using analog ICs. Apply for a donation of up to 10 ASLK boards for your University.
The suggested strategy solves the miscorrelation problem between the timing and the optimization tools in a way that helps avoid extra pessimism in the design, thus saving on area and power.
The development of high-frequency circuits is very demanding, in multiple dimensions; not least, in order to meet tight time-to-market schedules, the use of efficient development systems is a must.
Optimal clock structure is very important in SoC designs as it impacts every critical aspect of the IC. The article explains multiple such scenarios that VLSI designers need to be aware of while architecting or analyzing the SoC clocking in ASIC designs.
After years of promises that next year would be the year of ESL design, the knee of the curve is now behind us, EDA analyst Gary Smith declared at this year’s DAC.
Low power is not an absolute but is context-dependent, ARM CTO Mike Muller says.
Vendors and customers go slowly on cloud computing.
Handling late-stage IPs with a pseudo-hardening approach offers the best of both the ‘flat-’ and ‘hard-partitioning’ methodologies