An introduction to offloading CPUs to FPGAs: Hardware programming for software developers
Researchers from Poland explain how to move C code to an FPGA-base implementation in a course for software developers.
Tags: software developers
University engineering students: Win $10,000 Engibous Prize!
The TI Analog Design contest is now open! Register today to receive free products, discounted tools, and engineer to engineer design support with your team project. Your project need only include 3 TI Analog IC’s or 2 TI Analog IC’s and a TI processor for a chance to win $10,000, $7,500, or $5,000.
Tags: TI Analog Design contest, team project
FPGA debugging techniques to speed up pre-silicon validation
This paper talks about some debugging techniques for FPGAs that can be adopted to speed up the validation process while at the same time highlighting some of their constraints.
Smart power hook-up methodology for memories on SoCs
Meeting IR drop requirements on an SoC can often be a challenging task. This paper discusses a new hook-up methodology for memories on SoCs that can significantly reduce the worst IR drop on SoCs and also lead to improved performance.
More-than-Moore memory grows up
Moore’s Law may not be running out of steam, but it may be running out of money, as scaling to smaller geometries becomes more cost prohibitive.
Read BDTI’s Evaluation of Our Floating-Point DSP on Hardware
Download this white paper to read a performance evaluation of Altera’s FPGA floating-point digital signal processing (DSP) design flow on 28 nm hardware by BDTI, an independent technology analysis firm. Also, watch a preview of the white paper today!
Tags: white paper, design flow, independent technology analysis firm, Digital Signal Processing, performance evaluation
A novel approach for simulation of digital circuits using levelization
This paper discusses the concept of levelization, its challenges and a generic approach for simulation of digital circuits that can be used even for simulating designs that fail in normal levelized simulation.
Tags: digital circuits, levelized simulation, generic approach
Floorplanning: concept, challenges, and closure
Floorplanning not only captures the designer’s intent, but also reflects the challenges and opportunities that affect the entire design flow, from design to implementation and chip assembly.
Tags: chip assembly, design flow
Sponsored Link: Learn analog systems with TI’s Analog System Lab Kit
Designed for undergraduate engineering students, the ASLK PRO features 14 step-by-step experiments using analog ICs. Apply for a donation of up to 10 ASLK boards for your University.
Tags: undergraduate engineering
Managing the 8- to 32-bit processor migration
To prevent seemingly Lilliputian processor disparities from hatching a swarm of
bugs, application developers working in C must keep native processor size and
endianness in mind and write their code with an eye toward portability.
Tags: application developers