Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success
The traditional waterfall approach of SoC implementation can no longer guarantee a predictable schedule and reliable silicon. Upfront and thorough analysis, in every aspect of SoC development, is needed for today’s SoC designs.
Tags: predictable schedule, SoC development
Design for manufacturing and yield
Without increasingly sophisticated software, manufacturing at 28 nm has become highly problematic and yields uneconomically low. What can be done to enable this and smaller nodes to reach the desired yields?
Design for manufacturing and yield
Without increasingly sophisticated software, manufacturing at 28 nm has become highly problematic and yields uneconomically low. What can be done to enable this and smaller nodes to reach the desired yields?
ACE Awards Lifetime Achievement: Kathryn Kranen
They say that the EDA industry gets no respect, but UBM Tech has just changed that by awarding an EDA veteran with the 2013 ACE Lifetime Achievement Award.
Tags: eda industry, UBM Tech, Kathryn Kranen
ACE Awards Lifetime Achievement: Kathryn Kranen
They say that the EDA industry gets no respect, but UBM Tech has just changed that by awarding an EDA veteran with the 2013 ACE Lifetime Achievement Award.
Tags: UBM Tech, eda industry, Kathryn Kranen
Using 3rd party IP in ASIC/SoC design
This article outlines some of the best practices for using the 3rd Party IP ecosystem as well as some of the common challenges in integrating and using 3rd party IPs in today’s high-end ASIC/SoCs.
Using 3rd party IP in ASIC/SoC design
This article outlines some of the best practices for using the 3rd Party IP ecosystem as well as some of the common challenges in integrating and using 3rd party IPs in today’s high-end ASIC/SoCs.
Using 3rd party IP in ASIC/SoC design
This article outlines some of the best practices for using the 3rd Party IP ecosystem as well as some of the common challenges in integrating and using 3rd party IPs in today’s high-end ASIC/SoCs.
An introduction to offloading CPUs to FPGAs: Hardware programming for software developers
Researchers from Poland explain how to move C code to an FPGA-base implementation in a course for software developers.
Tags: software developers
An introduction to offloading CPUs to FPGAs: Hardware programming for software developers
Researchers from Poland explain how to move C code to an FPGA-base implementation in a course for software developers.
Tags: software developers