1) SemiWiki – best DAC trip report, awarded to two authors
2) Synopsys – DAC survey request
So, the moral of the story is: Attend DAC, write trip reports and fill out those EDA surveys.
Tags: survey request, design tools, moral of the story, trip reports
Physical effects of semiconductors are becoming more and more interrelated. Each design decision can create unintended consequences. In addition to the old problems generated by wire capacitance, engineers can no longer manually balance the myriad effects such as leakage current, inductive noise or IR drop. Manufacturing processes and environmental variation can render your functional chip useless or economically unviable. Market forces are creating demands of higher volumes at lower and lower price points. Investors are losing their appetite for risk and paying a premium for predictable success. Designers must walk a tightrope of price and performance to reach their time-to-market goals.
| | IC Validator: Automatic DRC Repair |
| | This paper presents how in-design physical verification with IC Validator enables Automatic DRC Repair (ADR), a novel capability that makes it possible for designers to automatically detect, repair and revalidate signoff DRC violations with negligible physical or timing impact, all within IC Compiler.
Paul Friedberg, Staff CAE |
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| | IC Validator: GDS Merge |
| | With today’s increasingly complicated design flows, creating a snapshot of a design’s full mask set to run physical verification at intermediate points during the design cycle, or in-design, presents many challenges. This paper presents an optimal approach to creating a working snapshot of a design’s complete mask data set for the purposes of in-design physical verification with IC Validator, Synopsys’ award-winning physical verification platform for advanced nodes.
Rich Santilli, Staff CAE |
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| | IC Validator: Physical Verification for Analog Designs |
| | Physical verification challenges of analog designs are different than the challenges of large digital designs. In addition to complex runset requirements, a tight interface to a parasitic extraction tool and an easy-to-use GUI are needed to use a runset effectively in an analog design environment. IC Validator, the latest generation physical verification tool, can be used to solve these issues. This paper addresses many of the physical verification requirements of analog designers and how they are met with IC Validator.
Al Blais, Global Technology Services |
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| | Minimizing Time to Complete a Hierarchical Design |
| | This paper addresses design exploration and planning in a hierarchical flow for larger SoCs and discusses techniques for achieving predictable design convergence without surprises.
Steve Kister, Technical Marketing Manager |
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| | SmartDRD Automated DRC Visualization and Correction |
| | SmartDRD is a new, innovative technology built into Galaxy Custom Designer™ Layout Editor (LE) for interactive DRC violation visualization, detection and correction, commonly known as design-rule-driven (DRD) editing
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| | Multicore and Distributed Processing With TetraMAX® ATPG |
| | Running automatic test pattern generation (ATPG) on a single processor may take a week or longer to complete, especially for very large designs and when testing at-speed fault models. Designers and test engineers need a straightforward way to reduce ATPG runtime by many factors and deliver working test patterns in days, not weeks.
Cy Hay, Product Manager |
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| | Improve Design Productivity with Quality Checks on IP Timing Constraints |
| | When combining intellectual property (IP) blocks from various sources, the chip-level implementation teams may not have the detailed IP knowledge required to develop timing constraints for the IP.
Michael Robinson, Senior Design Consultant, Synopsys Professional Services |
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| | Realizing Low Power IC Design: It Starts with the Clock Tree |
| | There are numerous techniques to achieve a low-power design and several approaches to structuring the flow. As a starting point, high performance designs require a benchmark proven low-skew, low-insertion delay CTS solution. Correlation to industry standard sign-off engines for accuracy and minimum data format translations are required to achieve fast design closure. The optimal solution includes complete low power capability throughout the design flow. This paper addresses low power design issues and includes technologies and techniques to achieve high performance, low power design goals.
Harvey Toyama, Synopsys Implementation Group |
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| | Clock Mesh for Mainstream Designs |
| | By its very nature, even the best conventional clock tree synthesis leaves both performance and variation tolerance potential on the table. Clock mesh offers the designer a means of achieving extreme high performance along with the avoidance of process variation effects. Long known as the clock distribution method for high-end microprocessors, clock mesh also offers significant variation tolerance. Clock mesh use to be an entirely manual, difficult to analyze technology, but new advances in clock mesh automation and analysis now enable it to be considered as a mainstream clock distribution solution.
Harvey Toyama, Synopsys Implementation Group |
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| | Advanced Design Challenges Make DFM-Friendly Routing A Must-Have |
| | Timing, area, power, and signal integrity have traditionally been the primary objectives of design technology, and the primary care-abouts for designers and CAD engineers. Increasingly manufacturability and yield have also become critical design objectives, and multiple design-for-manufacturability (DFM) optimization techniques have been added to the design flows. As manufacturability has been a secondary goal, conventional routers have been optimizing for it after timing optimization – the point at which all of the primary design goals have already been met. While this methodology has worked well up to the 65nm technology node, it starts to break down at 45nm and below. This paper talks about the routing challenges at 45nm and below and the need for modern DFM-friendly routing technologies for achieving better manufacturability and higher yield without sacrificing performance.
Maria Gkatziani, Synopsys Implementation Group |
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| | Realizing a Scalable Hierarchical Design Flow: What’s Needed for Large Designs |
| | Today’s system on a chip (SoC) designs continue to get larger and more complex. Given that consumer products are now the main driver for SoC designs, design teams must deliver chips quickly to capture as much revenue as possible from the latest consumer trend. Flat implementation flows are inefficient in terms of computer system resource requirements and runtimes for large SoC designs. Teams are turning to hierarchical design flows to implement these designs. This paper discusses design exploration and planning in a hierarchical flow for large SoCs and delves into efficient techniques that produce fast turn times and a concurrent physical implementation that enables predictable design convergence.
Steve Kister, Synopsys Implementation Group |
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| | Achieving Faster Time-to-Tapeout with In-Design Sign-Off Metal Fill |
| | Achieving correct-by-construction results during implementation significantly reduces time to tapeout and avoids schedule delays. This paper presents a pushbutton flow to generate timing-aware, signoff quality metal fill during place and route.
David Pemberton-Smith |
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| | Accelerating Physical Verification with an In-Design Flow |
| | There is a growing need for a concurrent physical design and physical verification flow, also known as an in-design physical verification flow. This flow improves the overall turnaround time and ease of use of the physical verification process. This paper provides a production-proven example of this flow.
Elango Velayutham |
The Discovery Verification Platform is an integrated portfolio of functional, AMS, formal, low-power and hardware-assisted verification tools. Discovery provides high performance, high accuracy and efficient interactions among best-in-class technologies including mixed-HDL simulation, mixed-signal simulation, assertions, coverage, testbench automation, verification IP, formal analysis, unified debug, equivalence checking and rapid prototyping. Discovery’s components support industry standards including SystemVerilog, SystemC, VHDL, UPF, OpenVera, Verilog-A, Verilog-AMS, SPICE, and more.
| | Using Digital Verification Techniques on Mixed-signal SoCs with CustomSim and VCS |
| | Graeme Nunn, Calvatec; Fabien Delguste, Adiel Khan, Abhisek Verma, Bradley Geden, Synopsys
A case study that explains the various aspects of a scalable and reusable methodology for verifying analog IP that can be applied to VMM/UVM, from verification planning to testbench implementation and coverage collection. |
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| | Accelerating Analog Simulation with HSPICE Precision Parallel Technology |
| | Robert Daniels, Sr. Staff Engineer, Synopsys Inc.; Harald Von Sosen, Principal Engineer, Synopsys Inc.; Hany Elhak, Product Marketing Manager, Synopsys Inc.
HSPICE Precision Parallel technology is a new multicore transient simulation extension to HSPICE for both pre- and post-layout of complex analog circuits such as PLLs, ADCs, DACs, SERDES, and other full mixed-signal circuits. HPP addresses the traditional bottleneck in accelerating SPICE on multicore CPUs with new algorithms that enable a larger percentage of the simulation to be parallelized, with no compromise in golden HSPICE accuracy. Additionally, efficient memory management allows simulation of post-layout circuits larger than 10 million elements. |
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| | High-performance, Parallel Simulation with VCS Multicore Technology |
| | This white paper provides a detailed overview of VCS multicore technology, which improves verification performance by taking advantage of advances in the compute infrastructure. VCS multicore technology cuts verification time in half by harnessing the power of modern multicore CPUs and allows designers to identify performance bottlenecks and distribute time-consuming activities across multiple cores for faster functional verification and debug. Automatic partitioning and load balancing, event synchronization and memory optimization make VCS multicore unique for high-performance functional verification. Multicore technology combines the speed-up from parallel computation with the industry-leading Native Testbench (NTB) compiler optimization technique to deliver unmatched verification performance for large-scale designs for chip-level and system-level verification.
Usha Gaira and Sanjay Sawant |
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| | Are We There Yet |
| | How do you know when you have run enough random tests? A constraint-driven random environment requires comprehensive coverage data, which often leads to information overload. Without an automatic way to associate pieces of coverage data with a particular feature-set in the test plan, the coverage report is only meaningful to the creator of the data.
Nancy Pratt Dwight Eddy |
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| | A Fully Reusable Register/Memory Access Solution: Using VMM RAL |
| | Register structure and memory modeling is a very complex task of any verification methodology. Building a zero time mirror to check the correct functionality of every field from every register and memory is usually a very time-consuming process which needs to be repeated for every design.
Paul Lungu, |
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| | Five Vital Steps to a Robust Testbench with DesignWare Verificatio IP |
| | Verification is one of the biggest challenges for System-on-Chip (SoC) designs, and traditional methods have run out of steam. Writing individual tests is impractical for today’s large, complex designs because the state space and number of test conditions is simply too large to code by hand, leading to insufficient test coverage.
Charles Li, Ashesh Doshi |
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| | Low Power Verification for Multi-rail Cells |
| | Multi-voltage designs have become increasingly common in order to achieve low power. Multiple supply rails are an essential part of multi-voltage designs. Assuming that all output pins in a logic cone are related to a single supply voltage can cause functional failures in silicon or excessive power loss. Consequently, verification tools need to understand the relationship between the driving voltage rails and the impact on each output pin to accurately resolve the logic values. Synopsys’ Eclypse solution provides an infrastructure to capture the necessary information and MVSIM and MVRC are able to use the information to accurately verify multi-rail designs and lead to silicon success. This white paper discusses the challenges faced with static and dynamic verification of multi-rail cells in the context of low power designs.
Prapanna Tiwari, Synopsys, Inc. |
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| | NanoSim: A Next-generation Solution for SoC Integration Verification |
| | The convergence of consumer electronics and personal computing continues to drive the need for more powerful, complex and highly integrated IC design, fabricated with the latest manufacturing technologies.
Geoffrey Ying |
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| | SystemVerilog for e Experts |
| | This document identifies the major differences between the e language as defined by the IEEE P1647/ D6 draft standard and the SystemVerilog language as defined by the IEEE Std. 1800™ 2005 standard. It explains the semantics of those differences and, where relevant, presents how similar functionality can be obtained using SystemVerilog.
Janick Bergeron Synopsys Scientist |
Tags: staff engineer, analog simulation, layout circuits, signal circuits, parallel simulation, product marketing manager, analog circuits
Cloud computing offers on-demand access to elastic, scalable computing resources, typically on a pay-as-you-go basis. This provides the opportunity to avoid large, up-front investments, often required for resource-intensive and unpredictable or highly variable workloads. Functional verification regression testing fits this profile, and providing access to functional verification resources on the Cloud allows you to address unforeseen resource demand peaks, and avoid unpleasant schedule or priority tradeoffs. You may also reduce schedules when needed by adding large quantities of surge compute resources (see Figure 1) without being constrained by your existing hardware or software infrastructure. For more information, please read our EE Times article “What Cloud Computing Offers the Electronic Design Community“.
| | Power Efficiency in the Cloud: The Energy Cost of Cloud-based Verification |
| | With today’s focus on energy conservation from LED light bulbs to electric automobiles, it’s no surprise that the power efficiency of cloud-based computing is also getting close scrutiny. Cloud computing promises to bring unlimited computing bandwidth to everyone, and coupled with secure, fast, and easy access, it provides a seemingly unlimited supply of compute horsepower, just in time, with perfect elasticity. In this paper, we take a look at a few of the details of cloud computing from the standpoint of energy efficiency, using functional verification of modern digital designs as our example.
Power Efficiency in the Cloud: The Energy Cost of Cloud-based Verification
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| | Security Considerations and Approaches in Cloud for EDA |
| | In 2011, the speed of business and complexity of SoC design is driving compute requirements for verification towards an even more elastic solution, such as those provided by Hybrid or Public Clouds, to meet peak verification. However, the security surrounding chip design source files is a major concern, and understanding how security risks can be managed in this new business environment is key when considering using an EDA Cloud. In this paper, we will cover some of these concerns and possible risk mitigation strategies at a high level.
Glenn Newell, Synopsys
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| | Economics of Cloud Computing: Considerations for Deployment of Design Verification on Secure Public Clouds |
| | Rapidly increasing gate size and complexity in the ASIC/SoC industry has fueled an exponential growth in verification demands. This has resulted in massive increases in hardware spends to support wildly varying demands. Cloud Computing’s ability to offer compute capacity on demand can help eliminate the need to large compute infrastructures in house. This paper examines all the economic decisions that must be considered when evaluating a Cloud Computing solution.
Lawrence A Vivolo, Synopsys
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| | Amazon Web Services: Overview of Security Processes |
| | Amazon Web Services (AWS) delivers a scalable cloud computing platform with high availability and dependability, offering the flexibility to enable customers to build a wide range of applications. Helping ensuring the confidentiality, integrity, and availability of our customers’ systems and data is of the utmost importance to AWS, as is maintaining trust and confidence. This document is intended to answer questions such as “How does AWS help me ensure my data are secure?”
Amazon Web Services
Tags: led light bulbs, ee times article, energy cost, focus on energy, power efficiency, software infrastructure
If yes, than does it contains any common information?
If yes, than what are those points?
Can i create this file manually(something which is specific be not mentioned and only common things described) and the cell libraries can automatically access the tech parameters as needed for them as these would be present in the lib cells also?
Tags: layout simulation, cell libraries
- if this is so than what kind of rework generally done for power-otimization especially?
- if these parameters are inter-linked than how the things than handled?
- clean-up done for recommended logic circuitry in the design hinder/change the power behaviour, if yes than to what extent?
- what is the general tolerence factor kept for the lowpower design?
Tags: functional verification, logic circuitry, initial findings
Synopsys is the leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare® IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP, embedded memories, logic libraries, configurable CPU/DSP cores and SoC infrastructure IP. In addition, Synopsys offers SystemC transaction-level models to build virtual prototypes for rapid, pre-silicon development of software. With a robust IP development methodology, reuse tools, extensive investment in quality and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk.
Simple Ways to Manage Different Clock Frequencies of Audio Codecs
The audio codec creates the interface between the digital host processor and the audio transducers, such as microphones and speakers. When embedded in a SoC as an IP core, an audio codec appears as a digital block to the internal interfaces and transparently handles all the off-chip analog transducers and inputs/outputs. On the internal digital interface, it is important to understand the aspects relating audio sample rates and clocks. The clocks required by the data converters on an audio codec depend on the audio material sampling rates as well as on the clocks available on the host application and SoC. The combinations are quite complex due to the multitude of audio sample rate options and available host clocks. To further complicate matters, in audio-video applications, the audio clocks need to also be synchronized with the video clocks required by the video data converters. The digital filters process the digital samples between the digital audio interface and the audio data converters, and therefore, can perform sampling rate conversions. This paper will review the functions of digital filters in audio codecs and will illustrate how they can be used to support interfacing in a multitude of sample-rates and clock environments. Carlos Azeredo-Leme, Analog Design, Senior Staff
Demystifying Non-volatile Memory IP: Selecting the Right NVM IP for SoC Designs Targeting Wireless, Analog, Micro-electro-mechanical Systems and Security Applications
As the use of non-volatile memory (NVM) intellectual property (IP), particularly reprogrammable NVM IP, expands beyond traditional embedded flash applications such as microcontrollers and into wireless, analog, micro-electro-mechanical systems (MEMS) and security applications, an entirely new audience of designers is integrating NVM. For these new users, there are various NVM IP usage models and solutions currently available that are optimized to meet the requirements of these different applications. When selecting the right NVM IP solution, designers must take into consideration the specifications associated with the NVM IP as well as its nuances and overall impact on the system-on-chip (SoC) design. Craig Zajac, Senior Product Marketing Manager
Sweet Sounding SoCs: Why Analog Audio IP Lowers Costs and Sounds Better than Digital PWM
When determining the trade-offs between application requirements versus area and power, selecting the right audio drivers has become a critical decision for SoC designers. Audio drivers must efficiently address a wide variety of loading conditions such as line loads, earphone and headset loads, passive loudspeaker loads and more. For many years, solutions consisting of a digital-to-analog converter and continuous time drivers have co-existed with digital-centric Pulse Width Modulation (PWM)-based solutions to address the breadth of different audio loads. Perhaps the most important reason associated with choosing a digital-centric PWM-based solution is the perception that being purely digital its silicon area cost is lower than the analog implementations. However, this whitepaper shows that digital-centric PWM-based solutions do at most offset cost from silicon area to external components while failing to address a multitude of equally important application requirements besides low cost.
João Risques, Product Marketing Manager
Understanding Clock Jitter Effects on Data Converter Performance and How to Minimize Them at the System Level?
This white paper shows that the characteristics of the sampling clock may determine the system performance, and that their effect is independent of the data converter that is being used in the system rather being a function of the characteristics of the signal being processed by the system (for example, its frequency). It also identifies the main sources of this clock uncertainty (clock jitter effects), providing guidelines and rules for system engineers to understand and minimize such effects, thus assuring system performance requirements. Manuel Mota, Technical Marketing Manager
Ethernet Quality-of-Service: New IEEE Specifications Driving a New Generation of Network Products
As designers look to their next-generation network designs, they are faced with a set of new challenges when developing products that incorporate the common Ethernet interface. To maintain Ethernet as a dominate and long-lasting network interface, the latest IEEE updates, which are targeted at improving networking systems’ Quality-of-Service, will be critical to meet the demands of the consumer. Lokesh Kabra, Senior R&D, Manager; John A. Swanson, Senior Staff, Marketing Manager
Debugging SuperSpeed USB Software Using Virtual Prototypes
Software is a critical component for the development of USB-based designs. In efforts to start software development early and to make it as productive as possible, design teams are often utilizing virtual and FPGA prototypes for software development prior to silicon. This white paper describes how virtual prototype use models for hardware/software verification and the integration of the LeCroy analyzer software into Synopsys’ DesignWare SuperSpeed USB verification environments help solve SuperSpeed USB IP development challenges. Frank Schirrmeister, Director, Product Marketing; Tri Nguyen, R&D Engineer
High Definition Video AFE: Far Beyond the ADC
Based on the importance of the video AFE as an essential part of nearly any consumer video product or personal computing display and on the need that these products deliver the highest-quality images, this paper explains that, although it is possible to implement a video AFE from a stand-alone ADC and a collection of separate analog components, the complex interactions between them make developing an optimized system a difficult task which can add significant delay and risk to a design cycle. These risks can be reduced using an optimized video AFE core from a third party IP provider ensuring your design delivers the best possible video quality and power efficiency in all of the operating modes. João Risques, Product Marketing Manager
Reverse Process Migration from 65nm to 130nm in Under Three Months
Normally, a design team will tackle a new project on a new, smaller-geometry process and realize the benefits of increased performance and lower cost per chip. This white paper addresses the reverse of this situation, in which a functioning 65nm analog and mixed-signal design is “blown up” to a 130nm process to help mitigate the higher mask costs of the smaller geometry. Bob Lefferts, R&D Group Director, Analog and Mixed-signal IP, Synopsys; Neel Gopalan, AMS CAE, Synopsys
Hi-Fi Audio: Unveiling the Hidden dBs
While looking at Hi-Fi Audio, high “dynamic range” is the most popular measurement used to assess whether an audio system is “clean” (providing high-quality audio experience), but should not be the only area of focus. This paper discusses dynamic range, the specification and hidden dBs that should be considered for the best audio experience possible. Joao Risques, Product Marketing Manager
How System-Level Trade-offs Drive Data Converter Decisions
For both analog-to-digital converters (ADC) and digital-to-analog converters (DAC), system-level specifications have a strong influence on several aspects of the converter’s design, including conversion rate, resolution, power dissipation and silicon area. With a special emphasis on broadband wireless applications, this white paper reviews the design trade-offs ranging from the converter’s sampling rate to the choice of single- or multiple-chip system partitioning.
Manuel Mota, Technical Marketing Manager
Improving I/O Virtualization Performance with PCI Express
This paper provides an introduction to the general concepts of virtualization and I/O virtualization (IOV). It also discusses how IOV is addressed within the PCI Express sepcification and how to support IOV with an existing PCIe interface. Additional topics include: Single-Root IOV, Function Level Reset, Alternative Routing ID and Address Translation Services. Scott Knowlton, Sr. Product Marketing Manager
SuperSpeed Your SoCs with USB 3.0 IP
This whitepaper provides a comparison between the USB 3.0 and USB 2.0 standards, highlighting the new capabilities and advancements that have been made with this next-generation SuperSpeed USB standard including: performance, cables and connectors, power efficiency, USB model differences, hardware and software functionality, new protocol layers and streaming. Dr. Robert Lefferts, R&D Director; Subramaniam Aravindhan, R&D Manager
Show Me the Next-Generation HDMI
Explore the basic concepts behind HDMI, the markets it serves and its leadership role in multimedia interfaces. In addition, this paper provides a tutorial on the new capabilities of HDMI 1.4 and its role in providing a richer, more straightforward user experience. Example case studies are also presented to illustrate how the HDMI Ethernet and Audio Return Channel (HEAC) feature simplifies cabling requirements. Manmeet Walia, Product Marketing Manager
DesignWare SATA AHCI Host Controller – Understanding Multi-Port Configuration and Performance
This whitepaper describes how to configure and connect the DesignWare® SATA AHCI IP core to the DesignWare SATA PHY in a multi-port AHB-based configuration. It provides an analysis of the expected throughput on each port based on assumed system parameters. The intent of this paper is to enable users to take this example and insert actual system parameters to come up with a performance estimate. Bjorn Widerstrom, Corporate Applications Engineer
Embedded DDR Interfaces: Ten Tips to Success for Your SoC
Emerging from a host of competing technologies, DDR2 and DDR3 SDRAM (“DDR”) have become the dominant off-chip memory storage solution for SoC designs. Unfortunately, many SoC designers are unfamiliar with the realities of the DRAM standards, typical DRAM applications and the DRAM market. This paper presents ten guiding principles for embedded DDR interfaces, many of which the DRAM standards and vendor data sheets do not explain. Graham Allan, Sr. Product Marketing Manager
Enabling Portable, Lower Power HDMI-Based Designs with Interface IP
By using IP, SoC designers can easily incorporate an HDMI interface in leading edge process technologies such as 90 nanometer (nm), 65 nm and 40 nm processes. This eliminates the need for a separate IC, delivering significant power and cost savings. This paper provides an overview of HDMI standard , how it’s different from other digital video connections and the advantage of incorporating it into your SoC. Luis Laranjeira, Sr. R&D Manager
Meeting Timing Budgets for DDR Memory Interfaces
This paper provides a brief discussion of DDR source-synchronous timing concepts and describes five different timing domains. It shows how designers can meet timing budgets for double data rate, single data rate and cross-domain (clock-to-strobe) timing domains. Finally, it shows how to improve interconnect timing by reducing crosstalk, inter-symbol interference, reflections and skew as well as controlling simultaneously switching output (SSO) effects. John Ellis, Senior Staff R & D Engineer
Solving the Integration Challenges for USB-Enabled Designs
With power consumption and small form factors key issues, SoC designers must consider new requirements imposed by smaller technology nodes, especially for the USB PHY. This paper provides insights into dealing with these issues and profiles the USB IP offerings available from Synopsys. Gervais Fong, Product Marketing Manager; Eric Huang, Product Marketing Manager
Understanding the Fundamentals of PCI Express
PCI Express® – or PCIe® – is a high performance, high bandwidth serial communications interconnect standard that has been devised by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) to replace bus-based communication architectures, such as PCI, PCI Extended (PCI-X) and the accelerated graphics port (AGP). The objective of this white paper is to equip the reader with a broad understanding of the PCI Express standard, and the design challenges associated with implementing the PCI Express interface into an SoC. Scott Knowlton, Product Marketing Manager
DDR SDRAM: A Low Cost, Yet Increasingly Complex Off-Chip Memory Solution for SoCs
As the number of SoC designs requiring an interface to external memory increases, the modern DDRn SDRAM memory interface (DDR, DDR2 and DDR3) offers security of supply, high storage capacity, low cost and reasonable channel bandwidth, but comes with an awkward interface and complicated controller issues. In this paper, learn about the ins and outs of the DDR interface. Graham Allan, Senior Product Marketing Manager
High Performance Connectivity IP: Avoiding Pitfalls When Selecting an IP Vendor
The demand for connectivity IP for high-speed serial busses such as USB 2.0, PCI Express®, SATA, DDR2 and HDMI is increasing as standard interfaces in applications such as single chip recordable DVD CODECs and MP3 players. In order to stretch battery life of these chips, the semiconductor technologies require ultra-low power derivatives of high-performance logic manufacturing processes, enabling production of very low-power chips for these mobile platforms and small-form factor devices.
Navraj S. Nandra, Director of Product Marketing
Physical Implementation Challenges in Your SoC Design
This paper discusses how using complete, integrated DDR2 SDRAM memory physical interface IP solutions can significantly reduce the risks, such as interoperability, associated with combining discrete memory subsystem blocks. David Wallace, Product Marketing Manager
Low Power USB 2.0 PHY IP for High-Volume Consumer Applications
The USB protocol has become a pervasive standard in the world of computing and consumer electronics. While few design teams would today contemplate designing their own USB IP this semiconductor IP is far from commodity silicon. Synopsys introduces a second USB 2.0 PHY IP product line (DesignWare® USB 2.0 nanoPHY), which has been further optimized for low power, area, manufacturing cost and system performance targeted at mobile and high volume consumer applications. This offers designers a choice of highly differentiated USB PHY cores for 0.13-micron processes and below. Gervais Fong, Product Marketing Manager
How A Complete IP Solution Speeds Time-to-Market and Reduces Risk for 10 Gigabit Ethernet Applications
This paper discusses the merits of IP for the growing 10G Ethernet market, and introduces Synopsys’ complete DesignWare® 10G Ethernet IP solution in the context of the technology and the target applications. It provides an overview of the market growth trends and highlights typical application areas for 10G Ethernet.
Geetha R. Arun, Program Manager
Agere/Synopsys: Integrating a PCI Express Digital IP Core into a Gigabit Ethernet Controller
This paper discusses the integration and system verification challenges encountered when integrating a PCI Express digital IP core into a Gigabit Ethernet design. Techniques for configuration of the PCI Express IP toachieve the lowest power, lowest latency and smallest memory size, as well as optimal system performance are presented
Jing-Fan Zhang, Director, Business Development, Synopsys; Fadi Saibi, Sr. Member of Technical Staff, Agere Systems
Accelerating Functional Closure: Synopsys Verification Solutions
This paper focuses on practical aspects of the verification process that can help reduce the time taken to reach functional closure. It is based on experiences of working directly with many leading edge semiconductor companies implementing modern verification technologies and methodologies. Since coverage is a measure of how effectively the design is being verified, this paper will address when and how to implement code and functional coverage, and use it to achieve functional closure.
Hemendra Talesara, Synopsys Professional Services; Neill Mullinger, Synopsys
Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog
Design teams are turning to advanced and unified verification methodologies that leverage multiple technologies to handle the biggest verification challenges. Constrained random verification leverages compute resources and functional coverage technology to provide more testing with less test code development. This paper, the first in a 2-part series, shows how to start performing constrained random verification quickly and easily with Synopsys’ DesignWare VIP and VMM for SystemVerilog.
Charles Li, Corporate Applications; Ashesh Doshi, Product Marketing
Advanced Techniques for Building Robust Testbenches with DesignWare® Verification IP and Verification Methodology Manual (VMM) for SystemVerilog
This paper is the second in a series and discusses the benefit of using constrained random verification and briefly recaps the first paper “Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog”. The primary focus of the discussion is on using advanced techniques with Synopsys’ DesignWare® VIP and VMM for SystemVerilog to build a robust, constrained random testbench. The techniques that will be discussed are: Constraints, Factories, Callbacks, Coverage and Scenario Generation. Charles Li, Corporate Applications; Ashesh Doshi, Product Marketing
Advanced Stimulus Generation with DesignWare Verification IP and Verification Methodology Manual for SystemVerilog
This paper shows how to perform advanced stimulus generation using DesignWare Verification IP (VIP) and Verification Methodology Manual (VMM) for SystemVerilog. It focuses on two key topics – Exceptions and Scenario Generation. Exceptions represent protocol deviations or injected errors. The ability to create scenarios with Scenario Generation, which are sequences of protocol activity, is the key to effectively testing and verifying the design. This paper goes into the details of successfully creating exceptions and generating scenarios. Charles Li, Corporate Applications
Reduce Power, Area and Routing Congestion – Analysis of a High-Performance On-Chip-Bus Interconnect
This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare® Interconnect Fabric for the ARM® AMBA® 3 AXI™ while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare® Interconnect Fabric used to meet the stringent timing requirements. Fred Roberts, Corporate Applications Engineer
IP Solutions for Synchronizing Signals that Cross Clock Domains
This paper explains the many types of synchronization issues that occur when clocks and data signals cross from one clock domain to another. In all cases, the issues covered here involve clock domains that are asynchronous with respect to one another. Along with each issue, one or more DesignWare® solutions are outlined. The topics and solutions include: basic synchronization; temporal event synchronization; simple data transfer synchronization; data flow synchronization; reset sequencing; and, related clock system data synchronization. Rick Kelly, R&D Manager
Implementing Floating-Point IP for the Right Accuracy and Quality of Results (QoR)
With a rich library of DesignWare® Floating-Point IP, chip designers have many implementation choices that can significantly affect the final QoR. These choices are especially important when using synthesizable IP, where good implementation choices can optimize the tradeoffs between area/delay and accuracy. This whitepaper describes several types of flexible tradeoffs available to designers, including the benefits of specifying complex floating-point operations rather than multiple separate operations. Alex Tenca, Engineering Project Leader
Enabling Rapid Adoption of the AMBA 3 AXI Protocol-based Design with Synopsys DesignWare IP
To successfully develop an AMBA 3 AXI protocol-based design in the shortest time requires a comprehensive set of synthesizable IP, verification IP and an automated method to assemble the entire SoC subsystem. The AMBA 3 Advanced eXtensible Interface (AXI) protocol builds on the benefits of the AMBA 2.0 standard offering greater performance and flexibility. But with this flexibility comes complexity. This paper shows how the DesignWare IP solution for the AMBA 3 AXI protocol enables designers to quickly and easily integrate high speed designs based on the AMBA 3 AXI protocol. Mick Posner, Product Marketing Manager
Designing Using the AMBA 3 AXI Protocol
This paper examines the advantages of the new AMBA 3 Advanced eXtensible Interface (AXI) protocol for an on-chip bus infrastructure, and how it revolutionizes the future of high-performance system-on-chip (SoC) interconnect. It also describes the AMBA 3 AXI protocol feature set that makes it suitable for the new high-performance, low-latency and low-power designs. Mick Posner, Product Marketing Manager; Darrin Mossor, Synopsys
Coding Guidelines for Datapath Synthesis
This document summarizes two classes of RTL coding guidelines for the synthesis of datapaths. The first class helps achieve functional correctness and intended behavior of arithmetic expressions in RTL code. The second helps datapath synthesis to achieve best possible quality of results (QoR). Reto Zimmermann, Principal Engineer
A Survival Guide for Selecting High-Quality IP
This paper will explore three important determinants of IP quality: (1) Functional Correctness – extensive configurability of digital IP for standards interfaces and how an IP vendor verifies across a very large number of configurations. (2) Interoperability –probably the single most important criteria for IP and mistakenly equated with compliance, which is required but not sufficient on its own. (3) Ease of Integration –IP that is difficult to integrate will lead to schedule risk and increased cost of the SoC design.
Ed Bard, Sr. Director, Product Marketing; Ralph Morgan, Vice-President, Engineering
The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator
While the IP landscape will always look different when seen through the eyes of SoC designers, integrators and IP vendors, these players gain a significant advantage if they see each others’ roles more clearly. This paper explores the perspectives of three such players and their approach to working with mixed-signal IP. After taking in each perspective, life with IP might be a little easier for everyone.
David Chiapinni, Asic Project Manager, Matrox; Massimo Vanzi, CEO, Accent; Navraj Nandra, Director Product Marketing, Mixed-Signal IP, Synopsys
Life Begins at 65 – Unless You Are Mixed-Signal?
The old school of analog designers, exemplified by pioneer Bob Pease, is becoming an extinct species. But the demand for analog/mixed-signal IP blocks has never been greater, especially at 65 nm and below. Can this demand be met by using externally designed 3rd party analog/mixed-signal IP? Or, is the implementation of revolutionary changes to traditional work flows and analog design processes a suitable option? This paper will answer these questions and more.
Navraj S. Nandra, Director of Product Marketing, Synopsys; Reimund Wittmann, NOKIA Research Center, Bochum, Germany; Massimo Vanzi, Accent, Vimercate, Milan, Italy
Implementing Physical Layer Connectivity IP in Deep Sub-Micron Technologies
The physical layer is responsible for the transmission of the raw bit stream over the physical transport medium and is the lowest layer within the OSI network model. With high-speed interfaces such as the serial protocols USB 2.0, PCI Express®, SATA, and DDR2, the PHY provides the bridge between the digital and modulated parts of the interface. The trend is to integrate these mixed-signal interfaces into SoC that are manufactured in digital logic deep sub-micron technologies with channel lengths of 65 nm and 45 nm. Navraj S. Nandra, Director of Marketing Mixed-Signal IP
Reducing AMBA-based SoC Design Time by More Than 50% Using coreAssembler™
This paper describes how using a knowledge-based IP design and verification flow with coreAssembler can greatly reduce the time needed to assemble, configure, verify and implement a configurable AMBA™ subsystem with IP architected and packaged for use and intelligent assembly and configuration. The focus of this paper will be on the assembly of the subsystem with synthesis, verification and packaging of the subsystem summarized.
John Swanson, Product Marketing Manager
Building a Total Quality Experience into Silicon IP: Delivering DesignWare® Silicon IP into SoC Designs
Now more than ever, developers of complicated system-on-chip (SoC) designs rely on silicon IP (SIP) both internally developed and from third parties to achieve their time-to-market goals. After nearly 10 years of practice, SIP vendors must deliver a “Total Quality Experience” to buyers. This paper will describe the best way to measure quality which is essentially through direct customer feedback. Kevin Walsh, Director of Product Marketing
Reverse Disaggregation—How Silicon IP Will Change the Semiconductor Supply Chain
This paper discusses how reverse disaggregation will drive the creation of a new supply chain for the development of a new generation of products, full featured and assembled at zero cost, and how IP will influence how the new supply chain is created, reversing the disaggregation that has marked the industry until now.
Kevin Walsh, Director of Product Marketing
As mixed-signal designs increase in size and complexity the limitation of traditional fast-SPICE tools have become more apparent. The latest breakthrough in the ADMS verification platform is ADiT, a fast-SPICE simulator developed and optimized specifically for nanometer mixed-signal applications such as PLL, DLL, DAC, ADC, LDO, SERDES, etc.
During this lab-intensive, half-day workshop you will gain first-hand experience evaluating ADiT – Mentor’s next-generation fast-SPICE simulator. Learn how you can benefit from ADiT as a stand-alone product or in conjunction with Questa ADMS as a robust fast-SPICE mixed-signal simulation solution.
Seating is VERY limited to maximize your learning experience, so submit your interest immediately to request your spot. Lunch and refreshments will be provided.
Tags: fremont ca, spice simulator, half day
Read on for trends in ASIC design & verification… Verification Trends
Tags: functional verification, interesting facts, walden rhines, mentor graphics
HercuLeS is named after the homonymous constellation and not after the demigod.
Some of its features:
1. Integer and fixed-point (VHDL-2008) arithmetic of arbitrary lengths
2. It is able to synthesize VHDL from code spanning across several C functions
3. Support for both the Synopsys “de-facto standard” libraries and the official IEEE standard libraries
4. Support of synchronous read ROM and RAM memories (directly mapped to FPGA block RAMs)
5. Functions can pass single-dimensional array arguments
6. Support of streaming outputs (producing a sample at a time)
You can either code your input in ANSI C or in a bit-accurate typed-assembly language called NAC (N-Address Code). Then, your input is converted to a series of CDFGs (Control/Data Flow Graphs), expressed as Graphviz graphs with user-defined attributes, which again are translated to VHDL code adhering to the FSMD (Finite-State Machine with Datapath) paradigm.
I would appreciate if you had a look at the sample files available at the website. They illustrate complete examples of automatically synthesized algorithms such as Bresenham’s line drawing algorithm, and the Sieve of Eratosthenes. Overall, eight complete examples can be found at the HercuLeS website.
There will be regular updates on the HercuLeS webpage (every 1-1.5 months). The October update, scheduled for 2011/10/11, will allow access to HercuLeS via a web interface!
But first I would appreciate feedback on whatever related to the HercuLeS webpage.
You can contact me at: nikolaos.kavvadias-at-gmail-dot-com.
Research Scientist, Hardware developer,
Ph.D., M.Sc., B.Sc.
Tags: control data flow, flow graphs, single dimensional array, array arguments, address code