Elecard announces the release of a new version of Elecard ARM Codec SDK.

May 15, 2013 by · Leave a Comment
Filed under: Design and Reuse 

Elecard announces the release of a new version of Elecard ARM Codec SDK.
View the full article HERE.

To receive a RSS Feed with a complete description, click here

Moving to SystemC TLM for design and verification of digital hardware

May 14, 2013 by · Leave a Comment
Filed under: Design and Reuse 

By moving to SystemC TLM as the design entry point, and by leveraging high-level synthesis in combination with IP reuse, designers can handle growing design and verification complexity, time-to-market pressures, power goals, and evolving design specifications…
View the full article HERE

Moving to SystemC TLM for design and verification of digital hardware

May 14, 2013 by · Leave a Comment
Filed under: Design and Reuse 

By moving to SystemC TLM as the design entry point, and by leveraging high-level synthesis in combination with IP reuse, designers can handle growing design and verification complexity, time-to-market pressures, power goals, and evolving design specifications…
View the full article HERE

Automated ECO Flow for overall cycle time reduction

May 14, 2013 by · Leave a Comment
Filed under: Design and Reuse 

Engineering Change Order or ECO is the process of inserting logic directly into the gate level netlist corresponding to a change that occurs in the rtl due to design error fixes or a change request from the customer. ECO is preferred as they save time and money in comparison to a full chip re-spin. Some of these ECOs come very late in the design cycle, some of them have high level of complexity involved and at such times the need for an automated tool becomes a necessity. The idea proposed in the paper addresses this very issue. With this idea even complex ECOs can be implemented automatically in lesser turnaround time.
View the full article HERE

Tags: , ,

Automated ECO Flow for overall cycle time reduction

May 14, 2013 by · Leave a Comment
Filed under: Design and Reuse 

Engineering Change Order or ECO is the process of inserting logic directly into the gate level netlist corresponding to a change that occurs in the rtl due to design error fixes or a change request from the customer. ECO is preferred as they save time and money in comparison to a full chip re-spin. Some of these ECOs come very late in the design cycle, some of them have high level of complexity involved and at such times the need for an automated tool becomes a necessity. The idea proposed in the paper addresses this very issue. With this idea even complex ECOs can be implemented automatically in lesser turnaround time.
View the full article HERE

Tags: , ,

The TV Studio Becomes a System

May 14, 2013 by · Leave a Comment
Filed under: Design and Reuse 

Change is sweeping across the video production studio. High-definition (HD), ultra-high-definition (UHD), video over coaxial cable (or “coax”), video over Ethernet, digital post-production: the gusts of change are relentless. And while the basic functions of the studio remain unchanged since the days when Walter Cronkite first turned his reassuring yet saturnine gaze toward a camera, the way these functions are implemented and the architectures in which they reside are all in directed turmoil.
View the full article HERE

Tags: , , ,

The TV Studio Becomes a System

May 14, 2013 by · Leave a Comment
Filed under: Design and Reuse 

Change is sweeping across the video production studio. High-definition (HD), ultra-high-definition (UHD), video over coaxial cable (or “coax”), video over Ethernet, digital post-production: the gusts of change are relentless. And while the basic functions of the studio remain unchanged since the days when Walter Cronkite first turned his reassuring yet saturnine gaze toward a camera, the way these functions are implemented and the architectures in which they reside are all in directed turmoil.
View the full article HERE

Tags: , , ,

TSMC plots system super chips

May 14, 2013 by · Leave a Comment
Filed under: Design and Reuse 

TSMC plots system super chips
View the full article HERE.

To receive a RSS Feed with a complete description, click here

TSMC plots system super chips

May 14, 2013 by · Leave a Comment
Filed under: Design and Reuse 

TSMC plots system super chips
View the full article HERE.

To receive a RSS Feed with a complete description, click here

Teledyne Acquires Axiom IC

May 14, 2013 by · Leave a Comment
Filed under: Design and Reuse 

Teledyne Acquires Axiom IC
View the full article HERE.

To receive a RSS Feed with a complete description, click here

Pages: Prev 1 2 3 4 5 6 7 8 9 10 ...684 685 686 Next

« Previous PageNext Page »